1. Field of the Invention
The invention relates generally to semiconductor integrated circuit devices and a method of designing a layout thereof and, more particularly, relates to power supply interconnection structures of semiconductor integrated circuit devices where logic circuit elements (standard cells) of uniform height and a large scale circuit block larger than they are arranged together, and a method of designing a layout thereof.
2. Description of the Background Art
Rapid progress is now being made in electronic circuit devices. There is an increasing tendency for an electronic circuit device of high performance and improved function to be developed in a short period of time. Therefore, it is also necessary to develop a semiconductor integrated circuit device of high performance and enhanced function in a short period of time, which is essential for development of such an electronic circuit device within a short time. It is common to use, in designing, an automatic layout and interconnection program in order to develop a semiconductor integrated circuit device within a short period of time. It is difficult to treat logic circuit elements of various shapes in creating a program if the automatic layout and interconnection program is used. Accordingly, shapes of logic circuit elements are standardized. Generally, a method (standard cell method) is employed in which the heights of logic circuit elements to be arranged and interconnected to each other are made uniform. An internal region of a semiconductor integrated circuit device is formed by stacking an appropriate number of logic circuit elements (standard cells) to be arranged in a row in a lateral direction.
Large scale integrated circuit devices (LSIs) are classified into custom LSIs and semicustom LSIs with respect to LSI layout design according to recent, common classification. A custom LSI has its whole structure or an internal block designed exclusively for the specific LSI. A semicustom LSI is designed using a library in which layout patterns designed in advance as common circuits are registered. The above-mentioned standard cell method is classified as a method of designing a semicustom LSI according to the definition.
The standard cell method is a kind of method of designing a semicustom LSI in which an LSI is designed using standard circuit block cells which are designed and registered in a cell library in advance. Each circuit block cell is arranged according to an automatic layout and interconnection program of a CAD system. Standard cells as standard circuit block cells to be registered in the library are normally of layout patterns of a simple logic gate and logic circuits such as flipflops and so on designed in advance. Once these standard layout patterns are designed and their operation with accuracy is verified by a simulation or experiment, they are registered in a data base so as to make up a cell library. The standard layout patterns have geometrical configurations of uniform height and variable width. In short, in designing a layout of an LSI according to the standard cell method, standard layout patterns are taken out from the library and arrangement and interconnection of each layout pattern are made by the CAD system.
FIG. 20 is a plan view showing an arrangement of a semiconductor integrated circuit device according to a conventional standard cell method. Referring to FIG. 20, a peripheral circuit 2 such as an input/output buffer circuit is provided in the peripheral portion of a chip to be a substrate of a semiconductor integrated circuit device 1. A plurality of logic circuit elements 4 of the same height are arranged in a row in the lateral direction in the internal region of the chip surrounded by peripheral circuit 2. Power supply branch interconnecting lines 7 and 8 of VDD potential and GND potential for supplying VDD potential and GND potential to each of logic circuit element 4 are connected to each logic circuit element 4. A certain number of power supply trunk interconnecting lines 9 and 10 required for designing are arranged on the left and right sides of the chip and in a region interposed therebetween, for supplying the potentials VDD and GND to power supply branch interconnecting lines 7 and 8, respectively. Power supply terminals for logic circuit elements 4 are provided on the left and right sides of logic circuit elements 4. Adjacent two logic circuit elements are connected to each other by means of a rectilinear power supply interconnecting line. As a result, a pair of power supply branch interconnecting lines 7 and 8 are formed for a row of logic circuit elements 4. Power supply trunk interconnecting lines 9 and 10 are provided for supplying necessary power to the plurality of upper and lower power supply branch interconnecting lines 7 and 8 which are appropriately provided. Though not shown in FIG. 20, relatively thin signal interconnecting lines are provided in a region outside of the row of logic circuit elements 4 or a region above the row of logic circuit elements 4. Furthermore, as for these power supply branch interconnecting lines 7 and 8 and power supply trunk interconnecting lines 9 and 10, basically, the interconnecting lines in the lateral direction are adjusted to form first interconnecting layers and the interconnecting lines in the longitudinal direction are adjusted to form second interconnecting layers for the whole device. Different interconnection layers are connected to each other by a connection hole formed at a desired position of an insulating layer between the interconnection layers. In this way, automation of arrangement and interconnection can be effectively and readily achieved by using a systematic method of forming a chip including power supply interconnecting lines.
However, a more improved performance has been strongly demanded in recent years, so that the need has arisen for developing a semiconductor integrated circuit device of improved performance and function within a short period of time. Under such circumstances, there is a need for forming a semiconductor integrated circuit device by arranging together a large scale circuit block which is large in scale to some degree and has a definite function and logic circuit elements of the same height, instead of using only logic circuit elements of the same height as in the conventional manner. The large scale circuit block is, in advance, made up of elements of high integration density so as to have a high performance. The large scale circuit block may be, for example, a memory (random access memory or read only memory), a PLA, a multiplier or the like. Such a large scale circuit block has its pattern already formed when arrangement and interconnection of the whole chip is performed. Also, then, the configuration of interconnecting lines and positions of terminals in the power supply system have been already determined in the large scale circuit block. Accordingly, in many cases, it is not necessarily easy to interconnect the power supply systems of the large scale circuit block and the adjacent logic circuit elements of uniform heights. As a result, the power supply interconnecting lines of the logic circuit elements and the large scale circuit block cannot be standardized, making it difficult to automate the interconnection.
FIG. 21 is a flow chart showing a method of designing the layout of the semiconductor integrated circuit device on which the large scale circuit block and the logic circuit elements are arranged together. FIGS. 22 to 24 are plan views showing the plane arrangement of the semiconductor integrated circuit device according to FIG. 21. The method of designing the layout of the conventional semiconductor integrated circuit device will now be described with reference to these drawings.
Referring to step 201 of FIG. 21 and FIG. 22, a peripheral circuit 2 including an I/O buffer circuit and so on is provided on the peripheral region of chip 1 to be the substrate of the semiconductor integrated circuit device.
Then, referring to step 202 of FIG. 21 and FIG. 23, functional cells are provided in an internal region surrounded by peripheral circuit 2. One large scale circuit block 3 and a plurality of logic circuit elements 4 of the same height, for example, are provided as functional cells.
Referring to step 203 of FIG. 21 and FIG. 24, power supply trunk interconnecting lines 9 and 10 for VDD and GND and power supply branch interconnecting lines 7 and 8 for VDD and GND are so provided as to be interconnected to each other between each logic circuit element 4 and large scale circuit block 3. In this case, interconnecting lines 15 for signals are also provided between logic circuit elements 4. Arrangement of the power supply interconnecting lines and the interconnecting lines for signals is made by the automatic layout and interconnection program.
Thereafter, a determination is made as to whether the arrangement of the power supply interconnecting lines and the interconnecting lines for signals made by the automatic layout and interconnection program meets a prescribed condition as shown in step 204 of FIG. 21. If the arrangement of the interconnecting lines does not meet the prescribed condition, rearrangement of the power supply interconnecting lines, the interconnecting lines for signals, functional cells, and the I/O buffer is performed as shown in FIG. 21. In this way, the trial-and-error is repeated and the power supply interconnecting lines and the interconnecting lines for signals are rearranged until the prescribed condition is met.
In accordance with the conventional method of designing the layout, however, if the power supply interconnecting lines are to be arranged by the automatic layout and interconnection program, thick interconnecting lines, for example, power supply trunk interconnecting lines 9 and 10 for VDD and GND are provided as being bent as shown in FIG. 24. As a result, more chip area is required in designing the semiconductor integrated circuit device having a prescribed logical function. Manual designing has been inevitably employed in order to control the increase of the chip area as much as possible.
Normally, interconnection includes rough interconnection and minute interconnection which are separately performed. It is possible to arrange interconnecting lines for signals and power supply interconnecting lines separately in the stage of rough interconnection. However, as the interconnecting lines for signals and the power supply interconnecting lines are arranged in a mixed manner in the stage of minute interconnection, even if the power supply interconnecting lines are designated as being rectilinear in the stage of rough interconnection, the power supply interconnecting lines are bent in the stage of minute interconnection.
Methods for solving the problem as stated above have been proposed, for example, in Japanese Patent Laying-Open No. 2-82552 and Japanese Patent Laying-Open No. 2-86145, in which a sufficiently wide annular power supply interconnecting line is provided around the large scale circuit block.
An arrangement of a semiconductor integrated circuit device according to the proposal of the above-mentioned article is shown in FIG. 25. Referring to FIG. 25, annular power supply interconnecting lines are provided as surrounding the circumference of large scale circuit block 3. The annular power supply interconnecting lines include power supply interconnecting lines 5 and 6 of VDD and GND for supplying VDD potential and GND potential, respectively.
FIG. 26 is an enlarged detail view of a portion XXVI surrounded by the broken line of FIG. 25. As shown in FIG. 26, the annular power supply interconnecting line of VDD is made up of a first VDD annular interconnecting line 51 including a first lateral interconnection layer and a second VDD annular interconnecting line 52 including a second longitudinal interconnection layer. The annular power supply interconnecting line of GND is made up of a first GND annular interconnecting line 61 including a first lateral interconnection layer and a second GND annular interconnecting line 62 including a second longitudinal interconnection layer. The first VDD annular interconnecting line 51 and the second VDD annular interconnecting line 52 are electrically connected to each other through a connection hole 53b formed in an interlayer insulating film. The first GND annular interconnecting line 61 and the second GND annular interconnecting line 62 are electrically connected to each other through a connection hole 63b.
Logic circuit elements 4a and 4b are provided with VDD terminals 47 and GND terminals 48 for supplying VDD potential and GND potential, respectively. In the logic circuit elements 4a and 4b, the two VDD terminals 47 and 47 and the two GND terminals 48 and 48 that are facing each other are connected together by means of the first interconnection layer in advance. A first lateral VDD branch lines 71 including the first interconnection layer is connected to each VDD terminal 47. A first lateral GND branch line 81 including the first interconnection layer is connected to each GND terminal 48.
GND terminal 48 of logic circuit element 4a is connected to the second GND annular interconnecting line 62 by the first rectilinear GND branch line 81. VDD terminal 47 of logic circuit element 4b is connected to the first VDD annular interconnecting line 51 by the first rectilinear VDD branch line 71. The first GND branch line 81 is connected to the second GND annular interconnecting line 62 through a connection hole 63a. However, connection of VDD terminal 47 of logic circuit element 4a and the second VDD annular interconnecting line 52 and connection of GND terminal 48 of logic circuit element 4b and the first GND annular interconnecting line 61 are not made by a rectilinear power supply branch line. That is, the first VDD branch line 71 connected to VDD terminal 47 of logic circuit element 4a is connected to a second longitudinal VDD branch line 72 including the second interconnection layer through a connection hole 73b. The second VDD branch line 72 is connected to the first VDD branch line 71 through a connection hole 73a. The first VDD branch line 71 is connected to the second VDD annular interconnecting line 52 through a connection hole 53a. The first GND branch line 81 connected to GND terminal 48 of logic circuit element 4b is connected to a second longitudinal GND branch line 82 including the second interconnection layer through a connection hole 83b. The second GND branch line 82 is connected to the first GND branch line 81 through a connection hole 83a. The first GND branch line 81 is connected to the first GND annular interconnecting line 61.
In this way, provision of wide annular power supply interconnecting lines around large scale circuit block 3 standardizes and makes easy connection of many power supply branch interconnecting lines of the logic circuit elements adjacent to the large scale circuit block and annular power supply interconnecting lines. That is, the power supply branch interconnecting lines are arranged rectilinearly. As shown in FIG. 26, however, part of power supply branch interconnecting lines must inevitably be bent to be interconnected. Accordingly, providing only annular power supply interconnecting lines leaves portions where the power supply interconnecting lines cannot be simplified or standardized.
FIG. 27 is a plan view showing another example of the conventional semiconductor integrated circuit device having annular power supply interconnecting lines provided thereon. FIG. 28 is an enlarged view of a portion XXVIII surrounded by a broken line in FIG. 27. Referring to FIG. 28, a VDD terminal 47 of a logic circuit element 4a is connected to a first VDD annular interconnecting line 51 by a first rectilinear VDD branch line 71 and a GND terminal 48 of logic circuit element 4b is connected to a first GND annular interconnecting line 61 by a first rectilinear GND branch line 81. VDD terminal 47 of logic circuit element 4b is connected to a second VDD annular interconnecting line 52 by the first VDD branch line 71 through a connection hole 53b. However, connection of GND terminal 48 of logic circuit element 4a and the first GND annular interconnecting line 61 is not made by a rectilinear power supply branch interconnecting line. That is, the first GND branch line 81 connected to GND terminal 48 of logic circuit element 4a is connected to a second GND branch line 82 through a connection hole 83a. The second GND branch line 82 is connected to the first GND branch line 81 through a connection hole 83b. The bent interconnecting line thus connects GND terminal 48 of logic circuit element 4a to the first GND annular interconnecting line 61.
Annular power supply interconnecting lines 51, 52, 61 and 62 shown in FIGS. 26 and 28 have almost the same width as the heights of logic circuit elements 4a and 4b. As the power consumption of large scale circuit block 3 is large, a wide power supply interconnecting line is provided in order to supply sufficient power. Accordingly, the space between the two power supply branch interconnecting lines connected to the logic circuit elements do not conform to the annular power supply interconnecting lines. As a result, the bent power supply branch interconnecting lines are required at the connections of the logic circuit elements and the annular power supply interconnecting lines as shown in FIGS. 26 and 28.
FIG. 29 is a plan view showing still another example of the conventional semiconductor integrated circuit device having annular power supply interconnecting lines provided thereon. FIG. 30 is an enlarged view of a portion XXX surrounded by the broken line in FIG. 29. Referring to FIG. 30, the widths of annular power supply interconnecting lines 51, 52, 61 and 62 are smaller than the height of logic circuit element 4 in this example. The first VDD annular interconnecting line 51 and the first GND annular interconnecting line 61 diagonally face a VDD terminal 47 and a GND terminal 48 of logic circuit element 4, respectively. Therefore, connection of VDD terminal 47 of logic circuit element 4 and the first VDD annular interconnecting line 51 and connection of GND terminal 48 of logic circuit element 4 and the first GND annular interconnecting line 61 are made by bent power supply branch interconnecting lines, respectively. That is, a first VDD branch line 71 connected to VDD terminal 47 is connected to a second VDD branch line 72 through a connection hole 73b. The second VDD branch line 72 is connected to the first VDD branch line 71 through a connection hole 73a. VDD terminal 47 is thus connected to the first VDD annular interconnecting line 51. A first GND branch line 81 connected to GND terminal 48 is connected to a second GND branch line 82 through a connection hole 83a. The second GND branch line 82 is connected to the first GND branch line 81 through a connection hole 83b. GND terminal 48 is thus connected to the first GND annular interconnecting line 61.
As shown in FIG. 30, also in the case where the annular power supply interconnecting lines diagonally face the power supply branch interconnecting lines on a potential basis, the power supply branch interconnecting lines are bent for connecting the annular power supply interconnecting lines and the logic circuit elements. As a result, arrangement of all the power supply interconnecting lines cannot be simplified or standardized.
Connection lines for large scale circuit block 3 and annular power supply interconnecting lines 5 and 6 are omitted in FIGS. 25, 27 and 29.
FIG. 31 is a plan view particularly showing connection of a large scale circuit block and annular power supply interconnecting lines in a conventional semiconductor integrated circuit device having the annular power supply interconnecting lines provided thereon. FIG. 32 is an enlarged view of a portion XXXII surrounded by the broken line in FIG. 31. Referring to FIG. 32, a VDD terminal 13 and a GND terminal 14 are provided in the large scale circuit block 3. A VDD annular power supply interconnecting line includes first VDD annular interconnecting lines 51 and second VDD annular interconnecting lines 52. The first VDD annular interconnecting lines 51 are electrically connected to the second VDD annular interconnecting lines 52 through connection holes 53a, 53b, 53c and 53d. A GND annular power supply interconnecting line includes first GND annular interconnecting lines 61 and second GND annular interconnecting lines 62. The first GND annular interconnecting lines 61 are electrically connected to the second GND annular interconnecting lines 62 through connection holes 63a, 63b, 63c and 63d.
VDD terminal 13 of large scale circuit block 3 is connected to the second VDD annular interconnecting line 52 by a VDD connecting line 11. VDD connecting line 11 is connected to the second VDD annular interconnecting line 52 through connection holes 53p and 53q. GND terminal 14 of large scale circuit block 3 is connected to the second GND annular interconnecting line 62 by a GND connecting line 12. GND connecting line 12 is connected to the second GND annular interconnecting line 62 through a connection hole 63p.
A VDD terminal 47 of a logic circuit element 4 is connected to the second VDD annular interconnecting line 52 by a first VDD branch line 71 extending in a lateral direction. A GND terminal 48 of logic circuit element 4 is connected to the second GND annular interconnecting line 62 by a first GND branch line 81. The first VDD branch line 71 is connected to the second VDD annular interconnecting line 52 through a connection hole 53e. The first GND branch line 81 is connected to the second GND annular interconnecting line 62 through a connection hole 63e.
In this way, connection of logic circuit element 4 and the annular power supply interconnecting lines is made by power supply branch interconnecting lines 71 and 81 extending in the lateral direction in the same way as the connection of large scale circuit block 3 and the annular power supply interconnecting lines. Accordingly, in some cases, configuration of connecting lines for the annular power supply interconnecting lines and the large scale circuit block becomes complicated depending on the relationship between a position of logic circuit element 4 and positions of VDD and GND terminals 13 and 14 of large scale circuit block 3. That is, as shown in FIG. 32, the configuration of VDD connecting line 11 is complicated in connecting VDD terminal 13 of large scale circuit block 3 and the second VDD annular interconnecting line 52. Therefore, in some cases, the connecting line for the large scale circuit block and the annular power supply interconnecting line is not provided rectilinearly. As a result, arrangement of the connecting lines for the annular power supply interconnecting lines and the large scale circuit block cannot be standardized.
In the conventional semiconductor integrated circuit devices, there was a problem that the power supply branch interconnecting lines connected to the annular power supply interconnecting lines could not be formed rectilinearly in order to supply VDD potential and GND potential to the logic circuit element since the power supply interconnecting lines were structured as stated above. Also, the connecting lines could not be formed rectilinearly in connecting the large scale circuit block and the annular power supply interconnecting lines. Therefore, it was difficult to simplify and standardize the arrangement of the power supply interconnecting lines.
In a case as stated above, as power supply branch interconnecting lines which are wider than general interconnecting lines for signals are formed to be bent in a complicated manner, integration density of the semiconductor integrated circuit device is decreased. Also, the impedance of the power supply branch interconnecting lines is increased, so that power supply noise is increased. Furthermore, since the power supply branch interconnecting lines and the connecting lines between the large scale circuit block and the annular power supply interconnecting lines cannot be formed into fixed configurations, it is more difficult to automate arrangement of various logic circuit blocks, power supply interconnecting lines and so on.